The following is a simulation for a
Common Emitter Amplifier Circuit.
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The single stage common emitter amplifier circuit shown above uses what is commonly called "Voltage Divider Biasing". This type of biasing arrangement uses two resistors as a potential divider network and is commonly used in the design of bipolar transistor amplifier circuits. This method of biasing the transistor greatly Voltage Divider Network reduces the effects of varying Beta, ( ? ) by holding the Base bias at a constant steady voltage level allowing for best stability. The quiescent Base voltage (Vb) is determined by the potential divider network formed by the two resistors, R1, R2 and the power supply voltage Vcc as shown with the current flowing through both resistors. Then the total resistance RT will be equal to R1 + R2 giving the current as i = Vcc/RT. The voltage level generated at the junction of resistors R1 and R2 holds the Base voltage (Vb) constant at a value below the supply voltage. Then the potential divider network used in the common emitter amplifier circuit divides the input signal in proportion to the resistance.
$V_B=frac{R2}{R1+R2}Vcc$
Then $V_{RE}=V_B-V_{BE}$ (assume $V_{BE}=0.7V$)
$I_E=frac{V_{BE}}{R_E}$
and
$I_E=I_C+I_B=(1+eta) I_B$
So $I_C=eta I_B=frac{eta}{1+eta}I_E$
Finally, $V_{CE}=V_{cc}-V_{RL}-V_{RE}=$ $V_{cc}-I_C R_L-I_E R_E>V_{sat}$
($V_{sat}=0.2V$)
You are welcomed to check out similar applet at
Common Emitter Transistor Amplifier
